Always AL-1000 two registers are involved as for addition or subtractionthe digits of both registers must be retrieved from core in one digit period. To this end, the digit period is doubled Always AL-1000 span two memory cycles figure 6. Within Always AL-1000 digit period the A and the B latches are alternately loaded under control of the GR flag, but, in addition, the Q flag is toggled, resulting in memory cycles affecting digits in, alternately, the X and Y[…]
