Source : TGDailyEven though the throughput of the busses between a CPU and its memory keeps increasing, this is still the major bottleneck for the performace in most computersystems.
That's why manufactureres invented the cache memory, with L(evel)1, L2 and sometimes L3 cache.
While the size of this L2 cache is still growing, these SRAM modules are requiring more and more transistors (storing a single bit typically requires 6 transistors).
Intel is now looking to replace these SRAM units with DRAM cells. These require only 2 transistors per bit, allowing us to achieve a way higher memory density, and/or even smaller CPU's.
Intel already succeeded in creating this type of cache at 2 GHz, assuring a 128Gb/s throughput
